Scalable Heterogeneous Multi-Core System Based On Globally Asynchronous Locally Synchronous (GALS)

Abstract

Heterogeneous multi-core system has extensive
helpfulness in today’s applications due to a elevated performance
and reduced amount of power consumption. Based on different
scalable and/or flexible architectures of heterogeneous multi-core
system we have been presented one synchronous core and second
GALS cores. First core is clocked core design is still by far the
most popular design methodology for digital system. Synchronous
core is well implicit and supported by the grown-up CAD tools.
Today digital systems are implemented as System-on-Chips (SoCs).
Second core is Globally Asynchronous Locally Synchronous
(GALS) core is a relatively new VLSI system design methodology.
That promises to combine these two different cores and generate
dual or multi-core system. This has the advantages of both
synchronous and asynchronous core designs.
It created by applying different structering strategy on the
synchronous core architecture.To draw comparisons; a general
purpose 8-bit synchronous core was first designed and then
converted into GALS core. Both the models were implemented in
VHDL using Xilinx ISE 13.3 software and simulated using lSim
tool.
The synthesis results show that under the same power consumption
and a small area, GALS core outperformed the synchronous
processor in terms of operating frequency which is approximately
double the frequency of its synchronous version. These two compare
with the combine multi-core system. Where different functional
blocks have different clock necessary according to their
requirements and operating frequencies. To the complete and whole
system distributing a high frequency global clock with low skew is
a difficult task demanding a lot of design effort, die area and power.