Comparative Analysis of Single Stage CMOS Operational Amplifier in Gate Driven and Bulk Driven Mode

Abstract

This paper presents a comparative analysis for the design
of a single stage CMOS operational transconductance amplifier. The
motive behind applying input from the bulk terminal is to reduce
power consumption. Moreover, due to continuous downscaling of
CMOS technology, the threshold at the gate terminal has not
reduced with the rate at which the supply voltage is reduced.Due to
this, input at the gate terminal becomes equal to or more than the
supply voltage which further violates the condition of saturation. To
overcome this problem, input has been applied from the bulk
terminal rather than the conventional gate terminal. This results in
lower unity gain bandwidth under the same load condition.
However, when load condition is lessened, unity gain bandwidth
improves. The OP-AMP has been designed for gain-bandwidth of
greater than 5MHz and gain of 40 dB. The load applied at the output
is 10 pF. In gate driven mode, the design after simulation exhibits a
unity gain bandwidth of 6 MHz and gain of 37 dB with 880 positive
phase margin. In bulk driven mode, the design after simulation
exhibits a unity gain-bandwidth of 2 MHz and gain of 28 dB with
800 positive phase margin. Computer aided simulation analysis is
shown for each simulation. Designs have been carried out on
backend tool of mentorGraphics using tsmc 0.18 um CMOS
process and 1.8V power supply. Schematic simulations have
been carried out using “Pyxis Schematic” and simulations
have been done using “Eldo”.