Design of Low Power Area Efficient Double Tail Comparator

A. Akshaya, B. Sridevi, C. Bini Joy


Comparator is fundamental building blocks in analog-todigital converters. CMOS comparator which has dual input, dual output inverter stage suitable for high speed analog-to-digital such as flash pipeline ADCs it require high-speed with small chip area low voltage and low power. In this paper a double tail comparator by using clock gating technique is designed in such a way to reduces the overall propagation delay by replacing a existing comparator with a proposed double tail dynamic comparator it reduces the power and voltage by increasing the speed. Without changing the design modified method replace some pair of transistors connected in parallel for proposed comparator due to mismatch in transistor pairs. The design is simulated by using Tanner EDA Tools. The supply voltage (1.2 V) while consuming 9μW in modified comparator. It is shown that in the modified comparator both the power consumption delay time are reduced.

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