Implementation of Reconfigurable Convolutional Encoder and optimum Adaptive Viterbi Decoder with Multibooting and Error Detection on FPGA

Prashant R. Pachlegaonkar, Pranita S. Yadav


The main goal of this paper was resource-optimized implementation of the decoder on the target platform. It is well known that data transmissions over wireless channels are affectedby attenuation, distortion, interference and noise, which affect thereceiver’s ability to receive correct information. Convolutional encoding with Viterbi decoding is a powerful method for forward error correction. Convolutional encoders and viterbi decoders are play important role in digital communication especially, When channel is noisy and introduces errors in transmitted signal, Wireless communication systems such as the third generation (3G) mobile system, DVB, Hiperlan 3GPPLTE, IEEE 802.11a WLAN, IEEE 802.26 intelsat IES-308/309 utilize some formulation of convolutional encoding usually decoded via viterbi decoder using multiple booting technique is designed. Today’s data reconstruction in digital communication systems requires designs of highest throughput rate. Look ahead technique is studied for extracting vectorized output bits without taking into consideration the hardware cost involved. It improves the throughput rate. Implementation parameters for the decoder have been determined through simulation and the decoder has been implemented on a Xilinx FPGA SPARTAN 3E Kit. VHDL language is used as a design entry. The architecture can be reconfigured to decode a range of convolutionally encoded data with ½ rate, constraints lengths varying from 2 to 8 and various generator polynomials. In the starter kit mentioned above, two designs are implemented on the flash memory using the multiple booting techniques, the convolutional encoder and the viterbi decoder. The FPGA is configured with the specified design depending on the loaded program from the parallel NOR PROM flash memory. Also, configurability allows use of same hardware to satisfy needs of channel. And also error correction and detection, With this way of configuration, the FPGA itself can operates as a convolutional encoder or viterbi decoder of variable constraint length depending on SNR conditions of received signal.

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A. J. Viterbi and J. K. Omura, “Principles of Digital Communications and Coding”, McGraw-Hill, NY, 1979.

A. J. Viterbi, “Convolutional codes and their Performance in communication systems”, IEEE Transaction Communication Technology, Vol.19, pp. 751-77, Oct. 1971.pp 260-269

J. H. Yuen, “Modulation and Coding for Satellite and Space Communications”, IEEE Procedings, Vol. 78, No. 7, pp. 1250-1266, July 1990.

B. Sklar, Digital Communications: “Fundamentals and Applications”, 2nd edition, Prentice-Hall, Upper Saddle River, N J, 2001.

G. C. Clark Jr. and J. B. Cain, “Error-Correction Coding for Digital Communications”, Plenum Press, NY, 1981.

S.V.Viraktamath, Dr.G.V.Attimarad, V.P.Gejji, Ravi. H “Error Control Mechanism Using CODEC”, International Conference on Communication Software and Networks 2009” (ICCSN 2009), February 27 - 28, 2009. Macau, China. Page No 549; 978-0-7695-3522- 7/09.

S.V.Viraktamath, Dr.G.V.Attimarad, “Impact of constraint length on performance of convolutional CODEC in AWGN channel for Image applications” has been published in “International Journal of Engineering Science and Technology(IJEST)”, Vol. 2(9), 2010, 4697-4701.

Abdulfattah Mohammad Obeid, Alberto Garc´ıa Ortiz, Ralf Ludewig and Manfred Glesner, “Prototyping of a High Performance Generic Viterbi Decoder”, 13th IEEE International Workshop on Rapid System Prototyping (RSP’02).

Hema .S, Suresh babu .V, Ramesh .P “FPGA Implementation of Viterbi Decoder” Proceedings of the 6th WSEAS Int. Conf. on Electronics,

Stefan Bitterlich and Heinrich Meyr (1993). “Efficient Scalable Architectures forViterbi Decoders”. Aachen University of Technology, Templergraben , Germany.pp 89-100.

Christian Schuler and GMD IOKH. “Code Generation Tools for hardwareimplementation of FEC Circuits”.

Xilinx, Inc., San Jose Calif., "Spartan-3E Field Programmable Gate Arrays", 2006.

”A Parallel Viterbi Decoder for Block Cyclic and Convolution Codes”,

Department of Electronicsand Computer Science, University of Southampton.April 2006.


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