A Review On Implementation And Performance Analysis Of ALU Using Various Clock Gating Techniques On Various FPGA Board

Vikas K. Jathar, P. C. Bhaskar


The need of time demands for development in high
speed and high performance Chip design systems in
networking or in communication and computing and this can
be achieved by designing and implementing of a latch free
Clock Gating Arithmetic and Logic Unit for obtaining in low
power processor design in the platform Xilinx ISE 14.5 and
Power analysis is carried out using Xilinx XPower
analyzer.In our proposed system, we are focusing on clock
gating approach to obtain reduction in clock power and total
power consumption in Arithmetic and Logic Unit and we
have analyzed power reduction on various Field
Programmable Gate Array devices. Clock power and total
power reduction by clock gating priciple in 16-bit ALU are
verified by XPower analyzer on 40-nm Virtex-6, 65-nm
Virtex-5,90- nm Virtex- 4, Spartan 3, Spartan 3E,Spartan-6
and Artix-7 target device.

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